Project Overview
The goal of this project is to provide a near-zero latency, fully pipelineable image compression scheme that can be mapped to an FPGA or ASIC. As of now, there is nearly zero latency performing convolutions on incoming data for image processing, but the amount of RAM is limited. We are looking to provide a very lightweight compression and decompression scheme that can be implemented at the input and output of each convolutional line buffer to reduce the amount of RAM needed. The end goal is to provide an RTL implementation on a Zynq Dev Board, and to deliver a demo with HDMI video into an FPGA, compression and decompression being performed on the live input stream. Ideally, a timer or clock will be displayed on the screen that provides real time latency information.Team Members
Kareem Eljaam
Client Interaction
I am a Computer Engineering student and I am focusing on low level programming in embedded systems. I currently work part-time with John Deere, which is the reason this project was brought up. My mentor at work had this project idea, and I was interested in working with FPGAs, so we ended up proposing this project.
Caleb Rock
Faculty Advisor Interaction
I am an Electrical Engineering student studying with a particular emphasis on Control Systems and Embedded Systems. My family farms in NW Iowa so I am excited to be working with John Deere at the intersection of Agriculture and Engineering.
Benjamin Meinders
Software Component Design Lead
Senior Majoring in Software Engineering, and Minoring in Music Technology. I was interested in this project after interning with CNH Industrial last summer, and wanted to extend my knowledge in the field of precision technology, and embedded systems.
Colsen Selk
Software Testing Lead
I am majoring in Software Engineering and I’m specializing in low level programming languages such as C. I chose this project because of the opportunity to work with John Deere to create a video compression system using hardware level and low level software that will be used by my family members who are farmers in central Iowa.
Logan McDermott
Hardware Testing/Component Lead
I am a Computer Engineering major from Cedar Rapids, Iowa who is hoping to specialize in Embedded Systems and Hardware Design. I chose this project because I wanted to contribute to John Deere’s mission of feeding the world while learning more about FPGA design.
Weekly Reports
Report 1Report 2
Report 3
Report 4
Report 5
492 Report 1
492 Report 2
492 Report 3
Design Documents
Team ContractTeam Preamble
Requirements, Constraints, and Engineering Standards Design Document
Project Plan
Engineering Design Document
Testing Design Document
Final Design Document
Final Documents
Final Design Document SE492Final Presentation SE492
Final Poster SE492